1. Field of The Invention
This invention generally relates to a processor and more particularly to a processor suitable for executing a conditional branch instruction at a high speed.
2. Description of The Related Art
Referring first to FIG. 3, there is illustrated the construction of a prior part processor. Reference numeral 1 designates an execution portion which has three pipeline stages for performing a processing on input data and outputs a result of the processing and a result flag representing the state of the result of the processing when receiving three clock pulses after the input data is inputted thereto. The result flag includes information representing information on "an EQUAL ZERO flag", "a PLUS flag" and "a MINUS flag" which will be described later. For simplicity of description, the number of the execution portion is assumed to be 1. Incidentally, the number of pipeline stages is also assumed for simplicity of description to be 3 but may be other than 3. Further, reference numeral 2 denotes an internal-state register for storing a code (hereunder referred to as an internal-state code) representing the internal state of the processor by using the result flag outputted from the execution portion
1. Reference numeral 3 designates an instruction-fetch-address generating portion for generating an instruction fetch address, which is comprised of a next address generating portion 4, a target-instruction-address generating portion 5, a selector 6 and a control portion 7 for controlling the selector 6. Usually, an instruction fetch address selected by the selector 6 is incremented by the next address generating portion 4. Then, the incremented address is outputted as the next address. When a branch instruction is executed, a target instruction address is generated by the target-instruction-address generating portion 5. Further, the generated target instruction address is outputted as an instruction fetch address. When a conditional branch instruction is executed, the control portion 7 determines from the internal-state code stored in the register 2 or from the result flag whether or not a corresponding branch is taken (namely, a corresponding branch condition is satisfied). If taken, the control portion 7 controls and causes the selector 6 to output a target instruction address.
Hereinafter, an operation (especially, the execution of a conditional branch instruction) of the prior art processor will be described by referring to the accompanying drawing. When a conditional branch instruction is used in a program, it is usual to employ a method by which an operation instruction is first executed and the internal-state code held in the register 2 is then changed according to the result of the execution of the operation instruction and subsequently it is determined from the internal-state code stored in the register 2 whether or not the branch is taken (namely, the branch condition of the conditional branch instruction is met). For example, an operation of the processor will be described hereinbelow when the following assembler instructions of an assembler program are executed:
______________________________________ . . . FMUL fr00, fr01, fr02 BRcc PLUS, lavel0 . . . ______________________________________
Namely, when the floating-point multiplication instruction FMUL is executed, the multiplication of data stored at the addresses fr01 and fr02 is first performed and then the result of the multiplication is stored in a location corresponding to the address fr00. Subsequently, the conditional branch instruction BRcc is executed. At that time, it is determined from the inter-state data changed according to the result stored at the address fr00 whether or not the branch is taken. In this case, if the PLUS flag is on, it is determined that the branch is taken (namely, the branch condition is satisfied). Thus, the program branches to the address lavel0.
Referring next to FIG. 4, there is illustrated the timing of operations of the prior art processor of FIG. 3 when this program is executed. The result of the operation (namely, the multiplication) effected by executing the FMUL instruction, as well as the result flag, is outputted when receiving three clock pulses after an input of data. Further, the BRcc instruction cannot be executed until the result is outputted. Namely, a wait cycle equivalent to two clock cycles is inserted between the input of the data and the execution of the BRcc instruction. Therefore, in case where a conditional branch instruction is executed in accordance with the internal-state code changed by performing an operation, the prior art processor as above constructed can determine a result flag only when the result of the operation is outputted. Consequently, the prior art processor cannot execute a conditional branch instruction only after an operation is completely accomplished. This has become an obstacle to the realization of a high-speed processing. The present invention is created to eliminate the above described drawback of the prior art processor.
It is accordingly an object of the present invention to provide a processor which can execute a conditional branch instruction at a high speed.